When the parallel port is configured to be bi-directional, are both data and control lines bi-directional?
A20. Only the data lines are bi-directional. In the ISA-compatible mode, even the parallel port data bus is uni-directional. The Nibble protocol permits data transfers from the peripheral device by using four peripheral status signal lines to transfer 4 bits of data at a time. Q21. Does the CFGINDX get over-written when the CFGTRGT is written? A21. The CFGINDX is an 8-bit register which contains the address index of the AIP configuration register to be accessed. CFGTRGT is a port for reading data from or writing data to the configuration register whose index address matches the address stored in the CFGINDX Register. Reading or writing the configuration target port does not over-write the configuration index register. Q22. What does the RESET do to the contents of the Configuration Index Register? A22. The CFGINDX Register has a default value of 00h following a RESET. Q23. Is the address decode for AIP resisters the full 11-bit decode inside the AIP for all of the registers? What about
