Referring to the Functional Timing Diagram in Figure B-21 on page B-20 (Appendix B) of the Technical Reference Manual, is it legal or illegal to give a new DMAC request while DMACCLR is HIGH?
It would not be legal to have another DMAC request from the SAME peripheral whilst DMACCLR is HIGH, as the DMACCLR signal is used as a handshaking mechanism to acknowledge the request and deassert the request once it has been serviced. It may, however, be possible to have a new DMAC request from ANOTHER peripheral whilst DMACCLR is HIGH. Thus considering an example of the sequence in question: 1) DMA{S/B}REQ goes active -> 2) data transfer -> 3) on last transfer DMACLR goes active -> 4) DMA{S/B}REQ goes inactive -> 5) DMA{S/B}REQ goes active indicating another transfer -> 6) DMACLR goes inactive. The difference between step-4 and step-6 is only ONE clock. In step-4 the request is inactive. On the very next clock DMACLR goes inactive (having sampled the inactive request) and the channel-state-machine goes to IDLE. After this happens, only then can the request come back again. In other words, the peripheral request should go low for at least ONE HCLK and only then can it can come back ag
