PLL_RESET serves two purposes, bypass and reset; how does one go about selecting BYPASS mode?
The RESET signal serves three purposes; first it holds the PLL in a reset state by forcing the VCO to operate at its minimum frequency. Second, it puts the PLL in a bypass mode such that PLLOUTA, B, C will be buffered versions of REFCK. Third, it initializes the phase alignment of PLLOUTA, B, C. RESET should be held active (high) during power-on until all of the following conditions are met: • All PLL inputs are stable and at their final values. • REFCLK is stable at or below the target frequency. • Any gating in the feedback path is removed. • VDDA and Vdd are at their final values. Failure to hold the PLL in reset (RESET=high) during power-on may result in VCO run away. In this mode, output clocks are not present and the PLL can be recovered only by pulsing the RESET or VDDA pins. A reset is also required should any of the PLL inputs change after power on. The minimum pulse width of RESET is 100ns.
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