Following a processor BR#, BG# was issued, but the processor did not initiate a transaction. Why not?
When designing external bus arbitration logic, note that the 750 family processors may assert BR# without using the bus after it receives the qualified bus grant. For example, in a system using bus snooping, if the 750 asserts BR# to perform a replacement copy-back operation, another device can invalidate that line before the 750 is granted mastership of the bus. Once the 750 is granted the bus, it no longer needs to perform the copy-back operation; therefore, the 750 does not assert ABB# and does not use the bus for the copy-back operation. Note that the 750 deasserts BR# for at least one clock cycle in these instances. Further, note that for the original 750 (Arthur) and the 750L, if the 750/L asserts ARTRY# due to a snoop operation, and asserts BR# in the bus cycle following ARTRY# in order to perform a snoop push to memory it may be several bus cycles later before the 750/L will be able to accept a BG#. (The delay in responding to the assertion of BG# only occurs during snoop pushe
