Xilinx Webpack, simulate with off-chip-connected-pins?
75658: 04/11/11: Re: Where to find very basic FPGAs 75678: 04/11/12: Re: asynchronous bus transfers 75679: 04/11/12: Re: I can’t set inout port in vhdl code 75761: 04/11/14: Re: asynchronous bus transfers 75762: 04/11/14: Re: asynchronous bus transfers 75763: 04/11/14: Re: asynchronous bus transfers 75764: 04/11/14: Re: Obsolete processors resurected in FPGAs 75805: 04/11/15: Re: Soft Processor Core 75906: 04/11/18: Re: Async and sync resets 76174: 04/11/27: Re: Spartan 3 output voltage level 76175: 04/11/27: Re: VLSI professional at NASA 76176: 04/11/27: Re: Quartus II: trace 76178: 04/11/27: Re: Choice of FPGA device — my view on benchmarks 76179: 04/11/27: Re: dual-write port BRAM with XST/Webpack 76186: 04/11/28: Re: dual-write port BRAM with XST/Webpack 76196: 04/11/28: Re: dual-write port BRAM with XST/Webpack 76198: 04/11/28: Re: XST question 76199: 04/11/28: Re: dual-write port BRAM with XST/Webpack 76258: 04/11/29: Re: dual-write port BRAM with XST/Webpack 76259: 04/11/29: Re