Xilinx webpack if – else if statement ?? From: “Marcel”
“rickman” wrote in message news:3D16A304.F767D0F@yahoo.com… > Duane Clark wrote: > > > > Marcel wrote: > > > Hi, > > > > > > I`m using Xilinx webpack and am quite new to VHDL, at the marked line I have > > > to place three times end if, > > > otherwise a syntag error is generated. > > > > > > Why do I have to place 3 times end if here instead 1 end if ? > > > > > > Any ideas ? > > > > > > > > > > > > process( SEL, D ) > > > begin > > > if ( SEL = “0000” ) then > > > TCK <= D(0); > > > else if ( SEL = “0001” ) then > > > > “elsif” instead of “else if”. > > > Marcel, > > Now you are supposed to say, “never mind”… 🙂 > I`ll just say thanks….
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“rickman”
