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Xilinx Webpack 9.1i.03 Verilog synthesis bug?

April 26, 2017bug synthesis verilog Webpack Xilinx

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Xilinx Webpack 9.1i.03 Verilog synthesis bug?

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Gabor: 66266: 04/02/16: Re: confused DCM clkin_period vs true input clock 66291: 04/02/16: Re: Xilinx Chipscope Sample rate 66292: 04/02/16: Re: IOB’s 76730: 04/12/09: Re: Verilog Book Recommendation 77041: 04/12/20: Re: PCB construction for PCI 77233

Xilinx Webpack 9.1i.03 Verilog synthesis bug?
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