Kicn:133669: 08/07/09: Configure registers of CMOS Sensor by Spartan3133694: 08/07/10: Re: Configure registers of CMOS Sensor by Spartan3kierenj:86347: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!86358: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!86443: 05/06/28: Re: Module integration, odd state machine behaviour (verilog), etc!:86333: 05/06/25: Module integration, odd state machine behaviour (verilog), etc!kil:122414: 07/07/27: regarding the post PnR timing simulation…..122424: 07/07/27: Re: regarding the post PnR timing simulation…..kilgor:111386: 06/11/02: Re: Implementing the Aurora Example Design V2.4(2.5) to a Virtex4111387: 06/11/02: Aurora v2.5 for V4FX – No “channel_up” in post-routed simulation during 200 us111436: 06/11/02: Re: Aurora v2.5 for V4FX – No “channel_up” in post-routed simulation during 200 us111466: 06/11/03: Re: Aurora v2.5 for V4FX – No “channel_up” in post-routed s