Would you give us an overview of IC packaging and SiP and how they related to SoCs, PCBs, …?
First of all, you have the traditional IC packaging. Typically in IC packaging you are taking a finished chip that has been fabricated, the wafer has already been sliced and diced. You are literally putting it into the package. You are designing the package as a physical layer entity. You obviously have to capture the layer connectivity between the correct pins on the chip and the correct balls, bumps, pins on the package. Then it is pretty much a straight constraint driven place and rout environment. That is where Cadence has been for quite a number of years. It is an Alegro package design solution. It has been pretty much focused on package layout construction for what I call backend chip whether those are analog, RF, SoCs, ASICs or maybe even memory chips. It is a matter of taking one or maybe more chips and assembling them together in usually the lowest cost package with the smallest form factor, bearing in mind such things as signal integrity. When system-in-package came around, i
