Why was the DS92LV18 LVDS Ser-Des designed to send an 18-bit payload, rather than the typical 8 or 16 bits?
Although data buses are often byte-oriented, many systems need to send extra information along with the data. Designers can use the extra bits of the DS92LV18 to conveniently send this extra information at the base data bus clock rate. As an example, a 8-bit/10-bit solution would require additional logic and buffering, twice the clocking rate (to accommodate the extra bytes), and a mechanism to add/drop comma (for synchronization) and idle characters (for rate adaptation). These features, and more, are built-in to the DS92LV18, simplifying the system design. In fact, some designers often take advantage of the two extra bits and use them for parity, flag, or control bits where only 16-bits of data transfer are required. Also, the DS92LV18 offers two extra bits, but the same package with the same pinout as its 16-bit counterpart, the DS92LV16.
Related Questions
- How much of the CPU bandwidth is consumed copying payload data across the socket API interface in send() or recv() system calls?
- Could the Vice Presidents comments though be designed to pressure Australia, to send more troops to Afghanistan?
- Are bypass capacitors required for systems designed with LVDS technology?
