Why there is only one record in the trace listing, if the dataselector hits on a misaligned access?
The dynamic dataselector of the ICE68020 detects any data pattern even if the CPU access is split into two buscycles. E.g. a LONG access to address 0x3 is split into a byte access to 0x3 and a tripple access to address 0x4. At the first buscycle (byte access) the data selector logic detects the first part of the data pattern. With the second buscycle (tripple access) the data selector detects the second part of the data pattern and becomes true. The first buscycle is not traced, because at this time the data selector does not “know” if the second part of the data access will hit the selector condition.
