Why might you want to use TestBencher Pro instead of writing a test bench by hand?
Surveys of VHDL users have indicated that generation of VHDL test benches typically consumes 35% of the entire front-end ASIC design cycle. It is clear that automation of test bench generation would significantly reduce the costs of VHDL-based design. TestBencher Pro provides an automated way for generating test benches. Some of the benefits of using TestBencher Pro are: Entering stimulus vectors in an HDL is time consuming and error prone Writing a VHDL or Verilog test bench is one of the most tedious and error prone parts of the simulation process. In HDLs you are required to specify the time for each signal transition. It is easy to make mistakes when writing an HDL test bench, because it is difficult when viewing the stimulus vectors in textual form to visualize the temporal relationships between transitions on different waveforms. For example it is difficult to tell if a signal transition on one signal occurs before or after a signal transition on another signal. However if you we
