Why is the master clock (MCLK) signal necessary for proper device operation?
A7. Because of the hybrid analog and digital nature of the line interface, the master clock signal present on the MCLK pin is necessary to operate both the clock- and data-recovery engine and the jitter attenuator. Without the master clock, the device would not be able to properly recover the clock and data signal present on the incoming line. The master clock signal is also used as an alternate recovered clock on the RCLK pin whenever the device enters a receive carrier loss state. To ensure that the device operates within specifications, the master clock should be derived from an accurate low-jitter source such as a crystal oscillator. T1/E1 devices usually use a source with a frequency tolerance rating of ±50ppm (or better) and a period jitter rating measured in picoseconds.
