Why is the ISA MASTER# signal not implemented on the PIIX3?
The PIIX3 supports ISA master initiated memory cycles to PCI and ISA master-initiated cycles to the internal PIIX3 ISA-compatible registers. PIIX3 will detect an ISA Master access when it asserts DACK# for a compatible DMA channel that is programmed in cascade mode (as all ISA bus masters DMA channels must be). In other words, if a device that is programmed for cascade mode DMA transactions asserts its DRQ, the PIIX3 will assume that it is an ISA Master. Therefore, the ISA MASTER# signal does not need to be implemented.
