Why is Stratus the optimum electroplating configuration for flip chip and 3D packaging?
Copper, nickel, and solder layers used in flip chip, WLCSP, and 3D processes are thick; even at high deposition rates, the deposition times are well over 10 minutes per wafer. To achieve high throughput, many wafers must be plating simultaneously. The Status system architecture allows for a line configuration that is readily matched to the multi-process requirements. For example, in a solder bump process, four copper and 16 solder wafers can be depositing simultaneously.
Related Questions
- Some of Freescales Flip Chip BGA packages do not contain lead (Pb) at the terminations (solder balls). Are these packages lead (Pb) free and RoHS compliant?
- Can the Intel® Pentium® III processor in FC-PGA packaging be used in a dual processing configuration with the 440BX?
- How do I include a custom manifest file in a packaging configuration ?
