Why does the Intel(R) JTAG Debugger provide a graphical representation of the page translation?
An OS or device driver developer may need to frequently access peripheral hardware devices and memory mapped configuration registers. Thus, while having code (OS initialization, driver kernel modules) executing in virtual memory space, they are accessing physical addresses and need to make sure that they either translate those addresses correctly in their code or that they exclude these memory areas used by peripheral configuration registers from any mapping. The page translation table view allows to see the memory setup for any address on your system at any given point in time by a simple mouse click. If you need to change the configuration on the fly you additionally have detailed access to the translation table entires and all the descriptor tables as well.
