Why does “masking capability” bit in PCIe Configuration MSI Control Status Register returns an incorrect value of “1”?
Solution The “masking capability” bit in PCIe Configuration MSI Control Status Register should return a value of “0”, as it is hardwired to ground. In simulation, it returns an incorrect value of “1” due to a bug in Quartus® II 9.0 SP2 software. The workaround is to use Quartus II 9.1 software. You can refer to Table 5-12 in PCI Express Compiler User Guide (PDF) for additional information about mask capability bit.
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