Why do CISC chips need to translate instructions?
you need to have N fully parallel threads worth of instructions to run which is pretty much the standard working load for any server OS. And on the desktop, with any modern CPU, available compute performance on any single task is typically grossly in excess of what’s required; it’s really only when multiple threads start contending that CPU performance becomes an issue. The architecture would have a certain amount of inherent “speed-step” in it too; with N-1 threads executing HALT and only one executing code, most of the chip would not be changing state most of the time, and power consumption ought to drop a fair bit. It’s a natural fit for stuff like codec graphs as well, so it might make a nice basis for a portable media player. Modern multi-core chips are moving to the model of simpler pipelines but lots of them which is not really what I’m advocating. I’m interested in the idea of a long and very piecewise single pipeline serving multiple interleaved sets of state, in such a way th
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