Why are the package lengths for BCLK[1:0] and Common clock signals not included in the Design Guide?
Please reference section 4.1 of the 4 Processor in 478-Pin Package and Intel® 845E Chipset Platform for DDR Design Guide. It states, “No length compensation is necessary” for the Common Clock line lengths. Section 4.2.2.1 also states “Common clock signals should be routed to a minimum pin-to-pin motherboard length of 3.0 inches and a maximum motherboard length of 10 inches.” Please reference section 11.2.1 of the same design guide. Table 11-3 provides all the necessary routing requirements for BCLK[1:0]. Note 1 states that “The skew budget includes… clock skew due to interconnect process variation,” which is internal skew due to package length. As long as these guidelines are followed, the package lengths are unnecessary.
