Why are all busses moving toward point to point routing architectures and not just higher speed multi-drop busses?
All end user applications will always demand higher and higher data rates, between chips, between boards and between cabinets. As data bandwidths have increased above the Gigabits/sec per channel rate, signal integrity limitations from the interconnects have forced a revolutionary change in transmission architectures. Reflection noise from stubs in parallel, multi-drop busses due to packages, termination resistors and routing constraints, limit the shortest rise times before noise is excessive to about 0.3 nsec rise times. CMOS technology has advanced into the regime where interconnects can’t keep up with the possible data rates using a parallel topology. When CMOS is capable of delivering higher data rates than the interconnect architecture can support, something has to change. Enter serial networks, where the interconnect topology is point to point. In this environment, signal integrity can be much more tightly controlled, opening up pathways with possible bandwidth limits well above
