Which to learn: Verilog vs. VHDL?
131182: 08/04/14: Re: case statements- verilog to vhdl 131188: 08/04/14: Re: case statements- verilog to vhdl 131220: 08/04/15: Re: Snythesis error 131222: 08/04/15: Re: asic gate count 131239: 08/04/16: Re: Snythesis error 131246: 08/04/16: Re: how do I test signals in a testbench that are 1 or 2 levels down 131268: 08/04/17: Re: Survey: FPGA PCB layout 131270: 08/04/17: Re: XST design frequency setting 131314