Which cycle times can we expect with CoDeSys?
The ability of CoDeSys to generate direct machine code consequently means it has full access to the hardwares performance capacity. A basic IL instruction results in one to three native assembler instructions which, in turn, add up to the following cycle times for 1,000 binary IL instructions: • Pentium 200 MMX 20s • 386EX 20 MHz 700s • 68332 20 MHz 600s • 80C167 20 MHz 570s • Dallas 80C32 20 MHz 1700s C code generation is roughly 20 to 30 % slower, the interpreter code is slower by a factor of 10.
