Where is a word forwarded after its read from memory?
A12.7: To the processor. Say there are 16 memory modules. They can all respond in the same cycle, but, depending on the design of the processor, it can probably receive only one or two words from memory at a time. Q12.8: When talking about caches are we to generally assume that all instructions are single-memory-reference instructions, so the miss ratio = 1 – hit ratio? A12.8: The miss ratio always = 1 – hit ratio. If I gave a definition that implied otherwise, I apologize. Q12.9: Would we need to know the percentage of, say, register-to-register instructions in order to figure hit ratio from miss ratio? A12.9: No. Q12.10: The cycle column has me completely confused. I don’t understand how you can access the addresses of the same row in the same cycle or for that matter how you can address ANY of them in the same cycle. A12.10: Simple. Memory is interleaved. They are 8 different memory modules (or “banks”). You can read a word from every module at the same time. Q12.11: On page B-21, i
