When the HT9200A/B is operating in the serial mode, are there any special considerations for the CLK pin?
Answer When the HT9200A/B is in the serial mode, the initial condition of the CLK line is high and the device uses the falling edge of the clock to latch in data. Therefore in the serial data mode, first setup the data, then the CLK pin should experience a high to low transition. After all the data has been transmitted, the CLK line should be returned to its initial condition otherwise the device will not generate the DTMF signal.
