When the configuration software probes my PCI slot, does it read my PROM 32-bits at a time, or one byte at a time?
The configuration space is read 32 bits at a time, but it is the option of the target to read it as 8-bit chunks. OBP reads the PCI ROM one byte-at-a-time on byte offsets. This is done partly to avoid any endianness issue. Note that on SBus, it was possible for the ROM to be wired for byte, halfword or word (32 bit) access (i.e. one valid byte per 32 bits). The card’s FCode would use the start0, start1, start2 or start4 FCode to signal to the host OBP how to address successive bytes when interpreting FCode. On PCI, the Expansion ROM is expected to be wired for byte access. The PCI ROM Header is accessed that way. Thus, when you get to the FCode image, the OBP pulls in the FCode one byte at a time, on byte boundaries.
