When I am using Export to program an FPGA I receive the error “startup clock for this file is CCLK instead of JTAG-CLK, problems will likely occur.” What do I do?
The configuration state machine inside the FPGA needs a “startup clock” to clock the final startup sequence after configuration. The startup clock source is controlled by an option setting in the “Generate Program File” process in the Xilinx ISE Project Navigator tool. The clock source should be set to JTAG-CLK to create a .bit file to be used for configuring the FPGA using a JTAG interface. The clock source should be set to CCLK for .bit files that are intended to be programmed into a Platform Flash. When building the project make sure that the startup clock is set appropriately. You can do this in Project Navigator by right clicking on the “Generate Program File” process. Select Properties and then click Startup Options. Set the startup clock to JTAG-CLK or CCLK as appropriate. The Xilinx iMPACT tool is capable of automatically setting the statup clock bit to JTAG-CLK if necessary during the programming process. Adept isn’t capable of changing the clock source “on the fly” and the pr
Related Questions
- The Bid4Build Program does not start after it has been installed and there is an error which mentions that the "MDE" file is not a valid file type. What does this mean?
- When I update the program from the website, I get an error message: "An error occurred while trying to replace the existing file: DeleteFile failed; Code 5." Why?
- Wood Beam Sizing has been working, but suddenly stopped with the message, Error in program file. What should I do?
