Whats the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
115008: 07/01/29: question about DCM usage in virtex 5 115016: 07/01/29: Re: question about DCM usage in virtex 5 115417: 07/02/09: uestion about “clock signal” in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING ) 115421: 07/02/09: Re: uestion about “clock signal” in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING ) 115445: 07/02/11: question about DCM in virtex5: fails the maximum period check 115480: 07/02/12: Re: question about DCM in virtex5: fails the maximum period check 115891: 07/02/23: Re: MicroBlaze and OPB block ram interface controller run at different frequency cationebox@gmail.