Whats the corresponding reset time for each reset mode on SPMC65 MCU?
No delay is needed after IAR and WDR. In POR mode, when the voltage is raised to 1.45V, the system will wait for 40ms for power supply stabilization and another 40ms for system clock stabilization and then 1024 system clock cycles the reset will be finished. LVR reset will occur when the power is lower than the certain level and if the power remained low for 1024 cycles of system clock. And it will be extended with additional 1024 cycles of system clock before the normal running. External reset will generate if the voltage of external reset pin is lower than 0.3xVDD and it remains low for more than 200ns. If the recharging voltage becomes acceptable, it remains a 40 ms for system clock stabilization and then additional 1024 cycles of system clock before the normal running.
