What type of decoupling is needed for clock devices?
We recommend following JEDEC recommendation by using the following filter circuit for AVcc: place the 2200pF capacitor close to the PLL, use a wide trace for the PLL analog power and ground, connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL), and recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8-ohm DC max, 600-ohm @ 100MHz).
