What part of JTAG standard is CPU agnostic?
JTAG specification is in Std IEEE 1149.1 (costs about $100). I don’t have it. Please search at internet for some JTAG related documents. This is good: http://www-s.ti.com/sc/psheets/ssya002c/ssya002c.pdf JTAG state machine [insert here] JTAG standard signal [insert here] That’s all! You just have to write software to go through the states of JTAG FSM (here is the state diagram of this FSM: http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-state-machine-large.png). TCK and TMS are used to go through the states of FSM. And TDI is used to serially send through this interface your commands and data to JTAG controller on the IC (in your case, to the ARM uC) and read back reply through the TDO pin. The only problem is that some companies do not open all details about available custom JTAG commands (JTAG standard defines only 2 necessary commands: EXTEST and SAMPLE and some optional commmands like INTEST, BIST and others). For example, Texas Instruments do not give an access to
