What Makes the DDR SDRAM Interface Sensitive to Package Choice?
Packaging decisions play a critical role in determining the success or failure of a DDR interface. Poor power delivery characteristics can lead to effects from simultaneously switching outputs (SSO) that slow down the circuitry and distort waveforms leading to timing margin erosion. This effect is highlighted in Figure 1 where the write data eye on the left shows the waveform with a minimum of SSO (only one data bit is switching, the remaining data bits are held at static levels) versus the write data eye on the right that shows all data bits switching concurrently representing the worst case SSO. The data signals shown in all of the data eyes in this paper were measured using the K28.5+ and K28.5- components of the compliance pattern defined for PCI-Express 2.0 that is designed to excite inter-symbol interference and jitter effects. The red trapezoid shown in each data eye presents the data eye width (valid logic levels) expressed in units of time based on clean transitions through VI
