What is the single-cycle Timed Loop?
The single-cycle Timed Loop (SCTL) is a special use of the LabVIEW Timed Loop structure. Timed Loop structures are always SCTLs when used in an FPGA VI. When used with an FPGA target this loop executes all functions inside within one tick of the FPGA clock you have selected. The default selection is the 40 MHz FPGA global clock. You can use the SCTL with derived clocks to clock the loop at a rate other than 40 MHz.
