What is the “READ CACHE x” instruction do on the SHARC DSPs?
The READ CACHE x instruction is effective only when the cache is disabled. When this instruction is executed, the contents of the CACHE entry x (any number between 0 and 31) are loaded into the registers CH, CL and CA. CH contains the most significant 24 bits of the 48-bit opcode that is stored in the entry x of CACHE. CL contains the least significant 24 bits of the 48-bit opcode. CA contains the address of the instruction that is cached. To read an entry of the cache, first disable the cache, then execute the read cache instruction, and finally reenable cache. The value of x denotes the combination of the set number and the way number.
