What is the maximum clock frequency?
Performance increases as n, n-k and the symbol width decrease. The examples in the data sheet can be used to give ballpark figures for your particular set of parameters. It is important that the core’s clock input, “clk”, is driven by a global buffer (“bufg”) component. This guarantees low clock skew and minimizes routing delays on the clock net. It is also important to set a maximum period constraint on the core clock input. The core asynchronous reset input, “reset”, should be driven by the global set/reset driver using the appropriate “startup” component. Information on driving GSR and “startup” components is available in the Xilinx on-line documentation. It may be possible to improve slightly on the values in the data sheet by trying different seed values for the place and route software. A seed value of 1 was used in the data sheet examples. The place effort level was also set to the maximum possible value. If necessary, performance can easily be increased by selecting a part with
