What is the jitter performance of the CDC7005?
• No jitter value is specified in our datasheet because the jitter performance depends on the reference clock and VCXO noise performance, CDC7005 PLL and loop bandwidth optimization. In the case of identical reference clock and VCXO, different jitter data has been observed due to different loop bandwidth settings. Phase noise performance is provided in the datasheet based on a particular VCXO as an example. If a better performing VCXO is used, better results will be observed. As an example, the CDC7005 with a 622.08 MHz VCXO, was found as having well below 500fs of rms jitter (from 12kHz to 20MHz).
