What is the impact of on-chip metal layers to silicon temperature distribution?
We have done some preliminary simulations by adding metal layers on top of silicon bulk. Due to the tiny cross-sectional area of the metal layer, and therefore the large lateral thermal resistance, we found that metal interconnects play a negligible role in laterally spreading heat within silicon. However, this is only our preliminary results, and we haven’t considered factors such as metal self- heating, busses, clock tree, etc. We are open to exchanging of ideas on this research problem, and would be glad to hear different voices.
We have done some preliminary simulations by adding metal layers on top of silicon bulk. Due to the tiny cross-sectional area of the metal layer, and therefore the large lateral thermal resistance, we found that metal interconnects play a negligible role in laterally spreading heat within silicon. However, this is only our preliminary results, and we haven’t considered factors such as metal self- heating, busses, clock tree, etc. We are open to exchanging of ideas on this research problem, and would be glad to hear different voices. • Can I use arbitrary grid size in grid mode? Not at this time. The current version of HotSpot only supports power-of-two grid size (e.g. 32*32, 128*64). This simplifies the implementation of the multigrid algorithm we used for grid-mode computation. If you would like to see a non power-of-two grid size please let us know and we may consider including that in a future release.
