What is the different between Behavioral and Post-Fit simulation?
Behavioral is a plain functional simulation, every logic will have (almost) zero delay. Post-Fit is a simulation after the fitting. This includes all delays in simulation. Fitting is the process of putting logic from your design into physical macrocell locations in the CPLD (Complex Programmable Logic Device). Routing is performed automatically. Q10: Error: “# XE version supports only a single HDL” This problem occurs in Xilinx v.8 and v.10. To fix: 1) Click the Sources tab in the Sources window. Make sure the “Source For:” is set to “Synthesis/Implementation”. 2) Select the schematic file, “filename.sch” 3) In the Processes window (Processes tab) below, click the plus sign next to “Design Utilities”. 4) Right click “View HDL Instantiation Template” and select properties. 5) Change the value from Verilog to VHDL. Click “OK”. 6) Repeat steps 4-5 for “View HDL Functional Model”. Or When you start a new project, make sure that you select “VHDL” instead of “Verilog” in the New Project Wiza
