What is the difference between VHDL and Verilog?
Fundamentally speaking, not a lot. You can produce robust designs and comprehensive test environments with both langauges, for both ASIC and FPGA. However, the two langauges approach the task from different directions; VHDL, intended as a specification langauge, is very exact in its nature and hence very verbose. Verilog, intended as a simulation langauge, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs. VHDL doesn’t let you get away with much; Verilog assumes that whatever you wrote was exactly what you intended to write. If you get a VHDL architecture to compile, it’s probably going to approximate to the function you wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has some features that make it good for system-level modelling, whereas Verilog is much better than VHDL at gate-level simulation. To confuse the situation more, see SystemVerilog…
