What is the cost benefit of using chips based on SPMT?
As consumers demand more rich features, mobile device manufacturers are faced with the challenge and expense of adding more processors to deliver this functionality – and that requires faster and denser memory. By shifting from parallel to serial interface technology, you can: • Reduce pin count by a minimum of 40 percent • Provide a bandwidth range from 3.2-6.4GB/s and higher • Reduce input/output power by 50 percent or more over other currently available DRAM offerings • Provide the ability to use either a single port or multiple ports into a single SPMT-enabled memory chip All of the above directly translate into lowering overall system cost.
