What is Silvus Source Code Methodology to migrate its IP to silicon?
The Silvus 802.11n MAC/PHY was designed as a silicon-ready IP core. It is a 100% synchronous design. Activity based clock gating of the major components provides automatic power management. Careful attention to signal processing design provides best in class SNR performance. The relatively low clock speed of the two clocks used by the design (80 and 120 MHz) made it possible to timing close the design at speed in the slowest version of a Virtex 5 FPGA. This provides assurance the design will perform from both a timing and functional perspective. A constrained, pseudo random, self checking test environment is provided to make it as easy as possible for the customer to verify proper instantiation of the 802.11n IP core. Customer integration requires the editing of only two VHDL files, one for all SRAM instantiations and a top-level wrapper which includes all clock and reset treatments. There are no synthesis, or scan test, unfriendly structures such as negative edge flops, latches, or as
