What is PowerQUICC microcode?
The PowerQUICC architecture integrates three main components: an embedded Power Architecture-based (PPC) Host Processor, a System Interface Unit (SIU), and a Communication Interface module (CPM). This dual-processor architecture consumes much less power than traditional architectures because the CPM offloads peripheral tasks from the embedded PPC core. The CPM is made of FIFOs, some protocol specific H/W, and a dedicated RISC processor. This RISC processor implements the various protocols requirements by running efficient programs from either the Freescale-supplied on-chip ROM (the “standard library”) or from an on-chip RAM. The CPM instructions are referred to as “microcode” instruction, and the programs are called microcode programs.
