What is Memory Reference Reuse Latency?
Memory Reference Reuse Latency (MRRL) refers to the distance (in completed instructions) between consecutive references to some memory location M[A]. By measuring the reuse latencies of each unique address accessed by a benchmark, we were able to select a point to begin cache and branch predictor warm up prior to each simulation sample cluster. Cache and branch predictor warm up assures accurate simulation; our delayed warm up technique achieves accurate simulation in less time than modeling all cache and branch predictor interactions prior to each sample cluster. For a more in-depth description, please refer to our technical report here and our ISPASS 2003 paper here. What’s the big picture and how well does MRRL work? Very briefly… MRRL works very well for sampled simulations, because MRRL-driven warm up eliminates nonsampling bias just as well as fullwarmup which models all pre-cluster instructions. Less briefly… Conte et al. showed that random cluster sampling is an approapriat
