What is cross probing?
This new feature introduced in Actel’s Designer Series R1-2001 Release establishes communication between Actel’s Timer, ChipEdit and Silicon Explorer for a complete debug loop. While evaluating the timing of critical paths in Timer, ChipEdit highlights automatically the placement of modules in these paths allowing observability of the relative placement of logic cells. From ChipEdit, users can call up the highlighted nets in Silicon Explorer to observe their real time values.
