What is a Makefile and how do I create one?
A Makefile is a plain textfile that is used to reduce repeatitive commands such as compiler invocation. All indentation in a Makefile should be done with tabs not spaces. A simple example of a Makefile is as follows and is invoked by typing ‘make’: all: gcc -Wall -O3 -o hello.exe hello.cpp The following is a more complex example that shows the use of variables and other features: # this is a comment SRC=hello.c main.c OBJ=$(SRC:.c=.o) # replaces the .c from SRC with .o EXE=hello.exe CC=gcc CFLAGS=-Wall -O3 LDFLAGS=-mwindows RM=rm %.o: %.c # combined w/ next line will compile recently changed .c files $(CC) $(CFLAGS) -o $@ -c $< .PHONY : all # .PHONY ignores files named all all: $(EXE) # all is dependent on $(EXE) to be complete $(EXE): $(OBJ) # $(EXE) is dependent on all of the files in $(OBJ) to exist $(CC) $(OBJ) $(LDFLAGS) -o $@ .PHONY : clean # .PHONY ignores files named clean clean: -$(RM) $(OBJ) core # '-' causes errors not to exit the process This Makefile can be invoked in any
• A Makefile can be thought of as a script that is processed by a “make” program. It allows large projects with many source files to compile in an automated way, as opposed to needing to compile each file by manually calling the compiler. It also allows for depedency checking, recompiling only modified files by checking timestamps.
