What is a low-level verification language?
Early versions of VHDL and Verilog were first released in 1985. In the succeeding 24 years there has, arguably, been only one significant development in commercial functional verification: the release of ‘e’ in 1996 (and, to a lesser extent, System Science’s Vera, at about the same time). These languages introduced or popularised a number of key verification methodologies, including the use of temporal assertions, constrained randomised stimulus generation, and coverage analysis. For any significant ASIC development, there’s little question that the use of the methodologies pioneered by these languages is fundamental to producing a Right-First-Time device. Given this, surely it’s clear that low-level verification – in other words, the verification of individual modules or limited groups of modules – should also be carried out using these languages, or their derivatives, such as SystemVerilog? Well… no. There are two very simple reasons: • These languages are primarily useful for syst
