What impact does this have on a traditional design methodology? Arent you just introducing yet another tool or step for already overburdened designers to have to deal with?
Actually, the Tela solution reduces the burden for designers in terms of thinking about DFM (design for manufacturability). The Tela solution is delivered as a physical design representation (GDSII) of a customers design IP. When synthesized and routed as part of the overall design, the solution enables a lithography-optimized layout. It works within standard EDA and physical design methodologies, and effectively hides the physics from designers for a streamlined implementation model.
Related Questions
- In synchronous chip design, designers commonly use Phase Locked Loops to deal with asynchrony across multiple voltage and clock domains. How is Elastix different from this?
- Do FPGA and ASIC designers have to change their design methodology and flow to use Tabulas ABAX 3PLD devices?
- What is design methodology and how will it impact my project?
