What design methodology is used for ProASICPLUS?
The ProASICPLUS design flow is the same as that used for an ASIC design or can also be designed using a FPGA flow. Our Designer software interfaces with synthesis tools from Synopsys, Cadence, Mentor Graphics and Synplicity. There are simulation interfaces with some of these same ASIC tool vendors and static timing support from Prime Time. The Designer software provides place and route along with timing. We also have an integrated tool suite with third party software available using our Libero software product.
