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What could be the reason for wrong exception vectors?

April 26, 2017exception vectors wrong

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What could be the reason for wrong exception vectors?

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The 68302 dual chip module uses two 68302 CPUs. Exception vectors are generated by the slave CPU which is in “disable CPU” mode. After reset no vectors will be generated because the VGE (Vector Generate Enable) of the System Configuration Register is disabled. This bit must be set by the user-program or by a data.set emulator command before the first interrupt is pending.