What constitutes a miss in a cache memory organization?
A10.1: A miss occurs when a line has to loaded into the cache from memory. Adding a new word to an existent line as in a fully associative cache is not a miss until the next line needs to be accessed. For example, if 4 words are being read in consecutively into an initially empty fully associative cache (which we’ll assume houses 4 words per line) constitutes only 1 miss and not 4. Q10.2: After reading more about caches in chapter 5, I think I might have misunderstood the concept about sectored caches. When you invalidate, do you invalidate just the line or the entire block for sectored caches? A10.2: You invalidate the whole sector. There’s only one tag per sector (to save on tag storage). When a new block from any other sector is placed in the sector frame in the cache, the tag is changed, and then there’s no way to find the old info that was in that sector frame, so it is invalidated.
