What causes stress to the silicon wafer?
Stress comes from three components: 1) Residual stress built into the UBM film as it was sputtered, plated or evaporated; 2) Stress that builds up in the films is due to microstructure changes as the film is thermally aged [e.g. solder reflow, High Temperature Storage]. This is most common on thick copper films; 3) CTE mismatch between material layers in the entire structure. The change in temperature causes each of the materials to expand or contract at different rates. The worst case condition is putting flip chips (CTE=3.5) onto FR4 (CTE=15-22). This causes localized strain mismatch that is seen as stress. All of the stresses are additive. Excessive stress can cause silicon fracture, bump fracture or lifting of the runners on the substrate. Some of the stresses in the bump are relieved as the solder bump creeps [stretches like chewing gum] to reduce the stress. Epoxy underfill is used to reduce the strain seen by the solder, which greatly increases its fatigue life. SnPb solders are
